1. Technical Field
The present invention relates to a tungsten plug structure of a semiconductor device and a method for forming the same, and more particularly, to a tungsten plug structure of a semiconductor device and a method for forming the same in which a tungsten plug process is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line.
2. Discussion of the Related Art
Attention has been focused on a metal line process based on copper to keep up with a semiconductor device of high speed. However, many efforts to use a metal line process based on aluminum are recently being tried considering economical and patterning aspects. Particularly, devices based on the aluminum metal line process in 130 nm technology are coming onto the market.
A method that makes multilevel metal lines and connects the multilevel metal lines in an integrated circuit is widely used as the size of the semiconductor device is gradually reduced. Generally, to connect the metal lines with each other, a contact hole is formed on a lower metal line layer and metal such as aluminum is deposited by sputtering to form an upper metal line layer. Thus, the multilevel metal lines connected with each other through the contact hole are completed.
However, if the metal such as aluminum is deposited by sputtering, the metal is not completely buried in the contact hole. For this reason, the metal lines are not connected with each other and step coverage in the contact hole becomes poor. As a result, problems occur in that contact resistance is increased and reliability is deteriorated.
In this respect, a metal plug based on tungsten having excellent burying characteristics of a contact along with excellent step coverage in a contact hole has been formed to connect the metal lines of the semiconductor device due to high integration of the semiconductor device. Tungsten has excellent step coverage characteristics in a direct contact and excellent burying characteristics in a metal contact.
However, with high integration of the semiconductor device, a design rule becomes strict and thus a sufficient margin in various processes is not obtained. Particularly, an aspect ratio of a tungsten plug is gradually increased and thus an overlap margin between the tungsten plug and the metal line becomes insufficient.
Hereinafter, a related method for forming a tungsten plug of a semiconductor device will be described with reference to the accompanying drawings.
FIG. 1A to FIG. 1D are sectional views illustrating process steps of forming a tungsten plug of a semiconductor device according to the related art, FIG. 2 is a sectional view illustrating a plug structure of a semiconductor device according to the related art, and FIG. 3 to FIG. 5 are sectional views illustrating problems of a plug structure of a semiconductor device according to the related art.
First, as shown in FIG. 1A, a silicon nitride (SiN) film (not shown) is thinly deposited on an entire surface of a silicon substrate 10 including gate electrodes 20 formed on the silicon substrate 10 at a constant interval. Boro phosphorous silicate glass (BPSG) or SiO2 is thickly deposited on the silicon nitride film by a chemical vapor deposition (CVD) process at a thickness of about 6000 Å to 10000 Å and then planarized to form an interlayer dielectric film 30.
Afterwards, as shown in FIG. 1B, the interlayer dielectric film 30 is partially dry etched using the silicon nitride film as an etching stopper to form a contact hole 40. As shown in FIG. 1C, tungsten is deposited on the entire surface by the CVD process and buried in the contact hole to form a tungsten plug 41.
Finally, as shown in FIG. 1D, tungsten is completely removed from the upper surface of interlayer dielectric film 30 by a chemical mechanical polishing (CMP) process to completely expose the interlayer dielectric film 30. Aluminum is then deposited on the entire surface including the tungsten plug 41 by sputtering and then patterned by a photolithographic process to form a metal line 50 that contacts the tungsten plug 41.
However, as shown in FIG. 2, an upper width W1 of the tungsten plug 41 is equal to the lower width W2. As shown in FIG. 3, a sidewall is etched simultaneously when the contact hole 40 is formed by the dry etching process. For this reason, the upper width W1 becomes wider than the lower width W2. As a result, an aspect ratio of the tungsten plug 40 formed by a gap-fill in the contact hole is increased. If the aspect ratio of the contact hole is increased, gap-fill of tungsten is easily made. However, it is difficult to obtain a sufficient margin due to high integration of the semiconductor device.
In other words, the aforementioned related art metal plug structure of the semiconductor device and the method for forming the same have several problems.
As described above, with high integration of the semiconductor device, the contact hole for formation of the tungsten plug has a narrow size. For this reason, a critical dimension specification (diameter of the contact hole) of the upper width W1 and the lower width W2 of the tungsten plug becomes tight. As a result, problems occur in that contact resistance between the tungsten plug and a lower metal line layer is increased and an overlap margin between the tungsten plug and the metal line is reduced.
At this time, as shown in FIG. 3, to minimize contact resistance between the tungsten plug 41 and the lower metal line layer (not shown), the contact hole suitable for the lower width W2 may be formed. In this case, the upper width W1 becomes greater and thus is wider than the width of the metal line 50. The tungsten plug below the metal line is externally exposed during etching of the metal line. For this reason, the tungsten plug may be corroded. Also, the tungsten exposed outside the metal line may flow to its adjacent metal line causing a short.
Meanwhile, as shown in FIG. 4, if the contact hole suitable for the upper width W1 is formed considering the overlap margin between the tungsten plug 41 and the metal line, the lower width W2 becomes small increasing contact resistance between the tungsten plug 41 and the lower metal line layer.
As shown in FIG. 5, if the aspect ratio of the tungsten plug 41 is increased, the gate 20 adjacent to the tungsten plug 41 may be corroded due to an etching gas when the contact hole is formed. In this case, a thin film transistor comprised of the corroded gate fails to perform its function.